1. Technical Field
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and method for driving the same.
2. Discussion of the Related Art
Conventionally, cathode-ray tubes (CRTs) may be used as display devices. Presently, much effort is being made to study and develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays (FED), and electro-luminescence displays (ELDs), as a substitute for CRTs. These flat panel displays may be driven by an active matrix driving method in which a plurality of pixels arranged in a matrix configuration are driven using a plurality of thin film transistors therein. Among these active matrix type flat panel displays, liquid crystal display (LCD) devices and electroluminescent display (ELD) devices are widely used for notebook computers and desktop computers because of their high resolution, ability to display colors and superiority in displaying moving images.
In general, an LCD device includes two substrates that are spaced apart and face each other with a layer of liquid crystal molecules interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the layer of liquid crystal molecules. The alignment of the liquid crystal molecules changes based on an intensity of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the electric field across the layer of liquid crystal molecules.
FIG. 1 is a schematic view illustrating an LCD device according to the related art. Referring to FIG. 1, the LCD device includes a liquid crystal panel 100 and a driving circuit. The driving circuit includes gate and data drivers 110 and 120, a timing controller 130 and a masking circuit 140. The liquid crystal panel 100 includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm crossing each other to define a plurality of pixels P. Each pixel P includes a thin film transistor T and a liquid crystal capacitor Clc. The liquid crystal capacitor Clc includes a pixel electrode, a common electrode and a liquid crystal layer between the pixel and common electrodes.
The timing controller 130 is supplied with synchronization signals to generate control signals to control the gate and data drivers 110 and 120. The timing controller 130 processes data signals and supplies those to the data driver 120. The gate driver 110 is supplied with control signals such as a gate shift clock (GSC), a gate output enable (GOE) signal and a gate start pulse (GSC). The gate driver 110 sequentially outputs gate voltages to the gate lines GL1 to GLn. The gate lines GL1 to GLn are sequentially enabled by one horizontal line, and the thin film transistors T connected to the enabled gate line GL1 to GLn are turned on.
The data driver 120 is supplied with the data signals and control signals such as a source sampling clock (SSC), a source output enable (SOE) signal, a source start pulse (SSP) and a polarity reverse (POL) signal. The data driver 120 outputs data voltages by one horizontal line to the data lines DL1 to DLm when the gate line GL1 to GLn is enabled.
The masking circuit 140 performs a masking operation according to a reset signal RE supplied from the timing controller 130. The masking operation is to make the GOE signal have a high level to block an output of the gate driver 110.
FIG. 2 is a waveform view illustrating a masking operation according to the related art. Referring go FIG. 2, when a reset signal RE has a high level, a masking operation is performed for a GOE signal. When the reset signal RE has a low level, the masking operation is not performed for the GOE signal. The reset signal RE has a low level when a power of the LCD device is off. The reset signal RE has a high level because the power is on. However, a predetermined time period may occur for the control signals for circuits to have a normal state. In other words, before the predetermined time period, even though the reset signal RE has a high level, the control signals may not have a normal state. Accordingly, there occurs an abnormal image display. For example, a screen of the LCD device may be displayed in a white or black.
To resolve this problem, the masking circuit (140 of FIG. 1) masks the GOE signal additionally during three or four frame periods from the power-on point, and then, when the control signals have a normal state, the gate driver (110 of FIG. 1) is made normally output gate voltages. In other words, during the low-level time period of the reset signal RE and the predetermined time period, the GOE signal (GOE_IN) input to the masking circuit is masked and the output of the gate driver is blocked. Then, the masking circuit outputs the GOE signal (GOE_OUT) as the GOE signal is input thereto.
Various events in the related art LCD device may have control signals supplied to the gate and data drivers that may not have a normal state during a predetermined time period from a starting point of the events, such as a channel change, an input signal change, a sound erasure and the like. However, when the various events happen, the abnormal image display is still caused in the related art LCD device.